1. Field of the Invention
The present invention relates to a driving circuit for performing driving control of a display device, a display device having the driving circuit and a driving control method of the display device.
2. Description of Related Art
In a Plasma Display Panel (hereinafter, referred to as “PDP”), it is essential to perform a floating operation due to problems associated with breakdown voltage characteristics of a scan driver.
All signals input to the scan driver need to be electrically insulated and, accordingly, insulating means are provided for this purpose. One example of the insulting means is a photocoupler, which is currently used in almost every PDP.
However, since the photocoupler is a very expensive device and a conventional PDP driving circuit requires a number of photocouplers along an input signal transfer path to the scan driver of the PDP, manufacturing costs of the conventional PDP driving circuit are increased considerably.
FIG. 11 is a signal processing block diagram of a conventional plasma display device 100.
Referring to FIG. 11, the plasma display device 100 is comprised of a PDP 101 which is a display unit for displaying an image, a control circuit 102 for controlling image display in the PDP 101, a first sustain discharge pulse generation circuit 103 for generating a sustain discharge pulse under the control of the control circuit 102 and outputting the sustain discharge pulse to the PDP 101, a second sustain discharge pulse generation circuit 104 for generating a sustain discharge pulse under the control of the control circuit 102 and outputting the sustain discharge pulse to a scan pulse generation circuit 107 (to be described later), a data driver 105 for transmitting display data to the PDP 101 under the control of the control circuit 102, a scan driver controller 106 under the control of the control circuit 102for controlling the scan driver, and a scan pulse generation circuit 107 for generating the scan pulse, outputting the scan pulse to the PDP 101, and driving a scan electrode of the PDP 101 under the control of the scan driver controller 106 and second sustain discharge pulse generation circuit 104.
FIG. 12 is a block diagram showing a partial structure of the scan driver controller 106 and the scan pulse generation circuit 107 in the plasma display device 100 shown in FIG. 11.
Referring to FIG. 12, the scan driver controller 106 is comprised of a first buffer circuit group 108 consisting of a plurality of buffer circuits 112, a photocoupler group 109 consisting of a plurality of photocouplers 113, and a second buffer circuit group 110 consisting of a plurality of buffer circuits 114. Further, the buffer circuits 112 included in the first buffer circuit group 108, the photocouplers 113 included in the photocoupler group 109 and the buffer circuits 114 included in the second buffer circuit group 110 are provided in equal number. For example, in the example shown in FIG. 12, 6 of each are provided.
Further, the scan pulse generation circuit 107 is comprised of a plurality of scan drivers 111.
The scan driver controller 106 generates control signals of plural kinds (for example, 6 kinds in the example shown in FIG. 12), such as a first blank signal BLK1, a second blank signal BLK2, a latch enable signal LE, a clear signal CLR, a data signal DATA and a clock signal CLK.
The scan driver controller 106 has signal transfer paths for respective control signals so as to output control signals of the plural kinds with respect to the scan driver 111 of the scan pulse generation circuit 107 in parallel.
That is, the scan driver controller 106 has, for example, 6 signal transfer paths, a first signal transfer path 121 functioning as a transfer path of the first clock signal BLK1, a second signal transfer path 122 functioning as a transfer path of the second blank signal BLK2, a third signal transfer path 123 functioning as a transfer path of the latch enable signal LE, a fourth signal transfer path 124 functioning as a transfer path of the clear signal CLR, a fifth signal transfer path 125 functioning as a transfer path of the data signal DATA and a sixth signal transfer path 126 functioning as a transfer path of the clock signal CLK.
The first to sixth signal transfer paths 121 to 126 have a buffer circuit 112, a photocoupler 113 and a buffer circuit 114, respectively, in the transfer direction of the control signal in the order described here.
The photocoupler 113 electrically isolates an upper stream side of the photocoupler 113 as the boundary from the downstream side thereof in each of the signal transfer paths 121 to 126.
Further, the first to sixth signal transfer paths 121 to 126 are connected to plural scan drivers 111, respectively.
FIG. 13 is a block diagram showing a construction of a conventional scan driver 111.
Referring to FIG. 13, the scan driver 111 has a shift register circuit group 131, a latch circuit group 132, and n output circuits 133 for outputting corresponding driving signals (scan pulses) with respect to n scan electrodes (gate electrodes) included in the PDP 101, respectively.
FIG. 14 is a timing chart showing signal waveforms of a control signal input to the scan driver 111 from the scan driver controller 106 and an output signal (scan pulses) from the scan driver 111.
Referring to FIG. 14, the scan driver 111 has, for example, a data signal DATA, a clock signal CLK, a clear signal CLR, a latch enable signal LE, a first blank signal BLK1 and a second blank signal BLK2 that are input to the scan driver 111. Further, the scan driver 111 outputs an output signal OUT, that is, a scan pulse to the scan electrode of the PDP 101.
Among them, the clock signal CLK, the clear signal CLR, the data signal DATA, the first blank signal BLK1 and the second blank signal BLK2 are input to the shift register circuit group 131, and the latch enable signal LE is input to the latch circuit group 132.
Further, the scan driver 111 inputs a high level (H) signal only to the DATA terminal of the shift register circuit group 131 initially, and then a low level (L) signal afterwards, as shown in FIG. 14. The data indicated by the high level (H) signal sequentially shifts an interior of the shift register circuit group 131 in synchronization with the clock signal input to the CLK terminal. At this time, the latch circuit group 132 is in the latch enable state, and the output of the latch circuit group 132 becomes a sequence high level (H) in synchronization with a shift of data indicated by the high level (H) signal in the interior of the shift register circuit group 131. As such, only one output out of the outputs of the latch circuit group 132 becomes the sequence high level (H).
As a result, n output circuits 133 output respective output signals OUT with respect to n scan electrodes (gate electrodes) included in the PDP 101.
Further, the following documents 1 and 2 are non-patent, exemplary technical documents for a conventional scan driver.
URL:    http://www.st-japan.co.jp/data/adv/20000406_prod1_pdp/pdf/stv7617.pdf found on the Internet on Sep. 8, 2004.
URL:    http://www.st-japan.co.jp/data/adv/20000406_prod1_pdp/prod1_pdp.html found on the Internet on Sep. 8, 2004.
In the conventional plasma display device 100, control signals of plural kinds such as a data signal DATA, a clock signal CLK, a clear signal CLR, a latch enable signal LE, and a blank signal BLK are transmitted from the scan driver controller 106 to the scan pulse generation circuit 107 in parallel, and the scan driver 111 is also configured on the basis of such parallel data transmission.
Accordingly, the scan driver controller 106 and scan driver 111 respectively required independent signal transfer paths to transmit the control signals of the plural kinds in the conventional art. That is, since there were so many control signals for the scan driver 111 to process, there were a correspondingly large number of signal transfer paths.
Furthermore, there is a need to arrange the photocoupler 113 on every signal transfer path.
Accordingly, it is not possible to prevent the size of the conventional PDP 101 driving circuit from being enlarged and it is not possible to reduce manufacturing costs thereof.